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OSDForum 2020 co-hosted by

OSDForum 2020 sponsored by

About OSDForum

The Open Source Developer Forum is a workshop that brings open source SW and HW (chips, boards and systems) developers together to collaborate and learn. The OSDForum includes talks from leading industry and academic experts focused on IoT, Edge and Machine Learning development leveraging open source SW and HW building blocks. The agenda also includes a hands-on session using a CORE-V MCU open-source RISC-V core FPGA development board. Made possible by the generous support of our sponsors, the OSDForum is a non-profit event with the low fee of $25 USD for industry and academic attendees. If you do not have a CORE-V MCU open-source RISC-V core FPGA development board, you can purchase a board and cable package at a discounted price of $150 USD plus shipping. Please indicate your interest in ordering a board during the registration checkout process.

The OSDForum is co-hosted by CMC Microsystems, the Eclipse Foundation and the OpenHW Group.

Agenda

Legend

  •   Standard Session
  •   Hands-on
  •   Break
Session Name Presenter Name Session Recording Slides
Standard Session Welcome, logistics, agenda outline, sponsor thank yous
Standard Session Open Source Processor IP - for High Volume SoCs Rick O'Connor (OpenHW Group) Session video for session Open Source Processor IP - for High Volume SoCs Session slides for session Open Source Processor IP - for High Volume SoCs
Standard Session Overiew of CORE-V CVE4, CVA6 & PULP Development at ETHZ Davide Schiavone (OpenHW Group) Session video for session Overiew of CORE-V CVE4, CVA6 & PULP Development at ETHZ Session slides for session Overiew of CORE-V CVE4, CVA6 & PULP Development at ETHZ
Standard Session ETHZ 'Arnold' Test Chip & the CORE-V MCU SoC Project Proposal
  • Brian Faith (QuickLogic)
  • Tim Saxe (QuickLogic)
Session video for session ETHZ 'Arnold' Test Chip & the CORE-V MCU SoC Project Proposal Session slides for session ETHZ 'Arnold' Test Chip & the CORE-V MCU SoC Project Proposal
Break 30min Break
Standard Session Overiew of CORE-V MCU & APU FPGA based platforms Florian Zaruba (OpenHW Group) Session video for session Overiew of CORE-V MCU & APU FPGA based platforms Session slides for session Overiew of CORE-V MCU & APU FPGA based platforms
Hands-on Being Productive with Open Source Eclipse Development Tools
  • Alexander Fedorov (ArSysOp)
  • Frédéric Desbiens (Eclipse Foundation)
Session video for session Being Productive with Open Source Eclipse Development Tools Session slides for session Being Productive with Open Source Eclipse Development Tools
Break 60m Lunch
Hands-on Using the CORE-V MCU FPGA platform Hugh Pollitt-Smith (CMC) Session video for session Using the CORE-V MCU FPGA platform Session slides for session Using the CORE-V MCU FPGA platform
Hands-on CORE-V IDE Roisin O'Keefe (Ashling) Session video for session CORE-V IDE Session slides for session CORE-V IDE
Hands-on CORE-V GCC Tools
  • Mary Bennet (Embecosm)
  • Pietra Ferreira (Embecosm)
  • Jessica Mills (Embecosm)
Session video for session CORE-V GCC Tools Session slides for session CORE-V GCC Tools
Standard Session CORE-V CVE4 in Bluespec RISC-V Explorer
  • Charlie Hauck (Bluespec)
  • Joe Stoy (Bluespec)
Session video for session CORE-V CVE4 in Bluespec RISC-V Explorer Session slides for session CORE-V CVE4 in Bluespec RISC-V Explorer
Standard Session RISC-V Chip for Mobile DNA Sequencing Dr. Sebastian Magierowski (York University) Session video for session RISC-V Chip for Mobile DNA Sequencing Session slides for session RISC-V Chip for Mobile DNA Sequencing
Standard Session Closing Remarks Rick O'Connor (OpenHW Group) Session video for session Closing Remarks Session slides for session Closing Remarks
Standard Session Adjourn